Characteristic evaluation apparatus for insulated gate type transistors

ABSTRACT

The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST 1.1 ). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST 1.6 ). From a shift amount (δ) which minimizes the standard deviation of the function F to be obtained (step ST 1.7 ), the true threshold voltage of the transistor with the narrow channel width is determined (step ST 1.10 ).

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. application Ser.No. 10/093,936 filed Mar. 11, 2002, now U.S. Pat. No. 6,559,672, whichin turn is a divisional application of U.S. application Ser. No.09/714,148, filed Nov. 17, 2000, now U.S. Pat. No. 6,373,274, which is acontinuation application of U.S. patent application Ser. No. 09/249,139,filed Feb. 12, 1999, now U.S. Pat. No. 6,169,415.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a characteristic evaluation method forinsulated gate type transistors which extracts their effective channelwidths, a characteristic evaluation apparatus for insulated gate typetransistors, a method of manufacturing insulated gate type transistorsby using the above characteristic evaluation method, and a computerreadable storing medium storing a characteristic evaluation program.

2. Description of the Background Art

An electrically effective channel width, i.e., an effective channelwidth W_(eff), can be determined from the drain currents of two or moreinsulated gate type transistors having the same channel length and adifferent channel width. This method is generally called “drain currentmethod.” The drain current method can directly determine the differencebetween an effective channel width W_(eff) and a mask channel widthW_(m), namely, a channel narrowing DW (=W_(m)−W_(eff)).

As a drain current method, a wide variety of methods have been proposedheretofore. They are described, for example, in “A New Method toElectrically determine Effective MOSFET Channel Width” by Y. R. Ma andK. L. Wang, IEEE Trans. Elect. Dev., ED-29, p. 1825, 1982; “A New Methodto Determine the MOSFET Effective Channel Width” by N. D. Arora, L. A.Blair and L. M. Richardson, IEEE Trans. Elect. Dev., ED-37(3), p. 811,1990; “A Method to Extract Gate-Bias-Dependent MOSFET's EffectiveChannel Width” by Y. T. Chia and G. J. Hu, IEEE Trans. Elect. Dev.,ED-38(2), p. 424, 1991; and “A Direct Method to Extract EffectiveGeometries and Series Resistances of MOS Transistors” by P. R. Karlssonand K. O. Jeppson, Proc. IEEE ICMTS, vol. 7, p. 184, 1994.

Of various drain current methods, Chia method is commonly often used.Thus, Chia method will be briefly described here. The total source-drainresistance R is given by the sum of a channel resistance R_(ch) and anexternal resistance R_(sd). Now, supposing the following Equation 1 asthe equation to express drain current: $\begin{matrix}{I_{ds} = \frac{\beta_{0} \cdot \left( {V_{gs} - V_{th} - \frac{V_{ds}^{*}}{2}} \right) \cdot V_{ds}^{*}}{1 + {{\theta 1} \cdot \left( {V_{gs}^{*} - V_{th}} \right)} + {{\theta 2} \cdot \left( {V_{gs}^{*} - V_{th}} \right)^{2}}}} & \left( {{Eq}.\quad 1} \right)\end{matrix}$

where β₀, V_(ds)* and V_(gs)* are given by the following Equations 2, 3and 4, respectively, and θ1 and θ2 are the invariables: $\begin{matrix}{\beta_{0} = \frac{\mu_{0}C_{ox}W_{eff}}{L_{eff}}} & \left( {{Eq}.\quad 2} \right)\end{matrix}$

where μ₀ is a carrier mobility, L_(eff) is an effective channel length,W_(eff) is an effective channel width, and C_(ox) is a gate insulatingfilm capacity:

V _(ds) *=V _(ds) −I _(ds) ·R _(sd)  (Eq. 3)

$\begin{matrix}{V_{gs}^{*} = {V_{gs} - \frac{I_{ds} \cdot R_{sd}}{2}}} & \left( {{Eq}.\quad 4} \right)\end{matrix}$

Neglecting the term of θ2, Equation 5 is obtained from Equations 1, 3and 4. Supposing an external resistance R_(sd) is inversely proportionalto an effective channel width W_(eff), a channel narrowing DW can beextracted through the following procedure: $\begin{matrix}{I_{ds} = \frac{\beta_{0} \cdot \left( {V_{gs} - V_{th} - \frac{V_{ds}}{2}} \right) \cdot V_{ds}}{1 + {\left( {{\theta 1} + {\beta_{0} \cdot R_{sd}}} \right) \cdot \left( {V_{gs} - V_{th}} \right)}}} & \left( {{Eq}.\quad 5} \right)\end{matrix}$

where the difference between a gate voltage and a threshold voltage,(V_(gs)−V_(th)), is defined as a gate overdrive V_(gt).

Step 1: Against a certain gate overdrive V_(gt), I_(ds)−W_(m)characteristic is plotted in an X-Y plane whose X-axis is mask channelW_(m) and Y-axis is drain current I_(ds), and a linear fitting, is made.At that time, the intersection with the X-axis in the X-Y plane which isobtained by extrapolating each straight line is the channel narrowing DW(V_(gt)) in the gate overdrive V_(gt) (see FIG. 1).

Step 2: By repeating step 1 while changing the gate overdrive V_(gt), itcan be seen how the channel narrowing DW (V_(gt)) depends on the gateoverdrive V_(gt) (see FIG. 1).

Prior art characteristic evaluation method for insulated typetransistors is constructed as described. In Chia method, for example, itis necessary to know the threshold voltage of a transistor for use inextraction. The threshold voltage of a transistor is found by, forexample, extrapolation from the characteristic between gate voltage andsource-drain current, as shown in FIG. 2. Therefore, the error due tothe uncertainty of a threshold voltage is further pronounced withreducing transistor size.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, a characteristicevaluation apparatus for insulated gate type transistors in which atleast two insulated gate type transistors that differ from each otheronly in mask channel width are used for evaluation and thecharacteristic of a first insulated gate type transistor having a widemask channel width serves as a reference, to evaluate the characteristicof a second insulated gate type transistor having a narrow mask channelwidth. This apparatus comprises: a threshold voltage estimation meansthat extracts the threshold voltage of the first transistor, estimatesthe threshold voltage of the second transistor, and employs a value asestimated, as a first estimated value; an extraction means in which (i)a difference between a gate voltage of the first transistor and theextracted threshold voltage of the first transistor is defined as afirst gate overdrive, and a difference between a gate voltage of thesecond transistors and the first estimated value is defined as a secondgate overdrive, (ii) in an X-Y plane whose X-axis is the mask channelwidth and Y-axis is source-drain conductance, a virtual point at which achange of Y coordinate value is estimated to be approximately zero whenthe first and second gate overdrives are finely changed, is extractedfrom a characteristic curve exhibiting a relationship between the maskchannel widths of the first and second transistors and the source-drainconductance, (iii) values of the X coordinate and Y coordinate at thevirtual point are defined as second and third estimated values,respectively, and (iv) a slope of the characteristic curve at thevirtual point is extracted and a value of the slope is employed as afourth estimated value; a threshold voltage determination means in which(i) from the second to fourth estimated values, optimum second to fourthestimated values are found with which the change of the third estimatedvalue is equal to the product of the change of the second estimatedvalue and the fourth estimated value, in reply to fine changes of thefirst and second gate overdrives, (ii) an optimum first estimated valueis determined which corresponds to the optimum second to fourthestimated values, and (iii) a true threshold voltage of the secondtransistor is determined based on the optimum first estimated value; anda channel narrowing determination means that determines a differencebetween the mask channel width and an effective channel width, based onthe true threshold voltage.

According to a second aspect, the characteristic evaluation apparatus ofthe first aspect is characterized in that the extraction meansapproximates the characteristic curve by using a first straight line inthe X-Y plane, the first straight line passing through a first pointthat is given to the first transistor when the first gate overdrive hasa first value and a second point that is given to the second transistorwhen the second gate overdrive has the first value.

According to a third aspect, the characteristic evaluation apparatus ofthe second aspect is characterized in that the threshold voltagedetermination means determines the optimum second to fourth estimatedvalues from a relational expression:${F\left( {\delta,V_{gtWi}} \right)} = {{{dW}^{**}\left( {\delta,V_{gtWi}} \right)} + {\frac{f\left( {\delta,V_{gtWi}} \right)}{f^{\prime}\left( {\delta,V_{gtWi}} \right)} \cdot {{dW}^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}} - {{DW}^{*}\left( {\delta,V_{gtWi}} \right)}}$

where δ is a difference between an estimated value of the thresholdvoltage of the second transistor, i.e., a first estimated value, and thethreshold voltage of the first transistor; V_(gtWi) is the first gateoverdrive; dW** is a value of an X intercept that is obtained byextrapolating the characteristic curve; f is the slope of thecharacteristic curve at the virtual point; DW* is an X coordinate valueat the virtual point; and a prime is the first-order differentiation ofV_(gtWi).

According to a fourth aspect, the characteristic evaluation apparatus ofthe second aspect is characterized in that the threshold voltagedetermination means determines the optimum second to fourth estimatedvalues from a relational expression:${F\left( {\delta,V_{gtWi}} \right)} = {{\frac{f^{2}\left( {\delta,V_{gtWi}} \right)}{f^{\prime}\left( {\delta,V_{gtWi}} \right)} \cdot {{dW}^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}} - {G_{m}^{*}\left( {\delta,V_{gtWi}} \right)}}$

where δ is a difference between an estimated value of the thresholdvoltage of the second transistor, i.e., a first estimated value, and thethreshold voltage of the first transistor; V_(gtWi) is the first gateoverdrive; dW** is a value of an X intercept that is obtained byextrapolating the characteristic curve; f is the slope of thecharacteristic curve at the virtual point; G_(m)* is a Y coordinatevalue at the virtual point; and a prime is the first-orderdifferentiation of V_(gtWi).

According to a fifth aspect, the characteristic evaluation apparatus ofthe second aspect is characterized in that the threshold voltagedetermination means determines the optimum second to fourth estimatedvalues from a relational expression:${F\left( {\delta,V_{gtWi}} \right)} = {{G_{m}^{**}\left( {\delta,V_{gtWi}} \right)} - {\frac{f\left( {\delta,V_{gtWi}} \right)}{f^{\prime}\left( {\delta,V_{gtWi}} \right)} \cdot {G_{m}^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}} - {G_{m}^{*}\left( {\delta,V_{gtWi}} \right)}}$

where δ is a difference between an estimated value of the thresholdvoltage of the second transistor, i.e., a first estimated value, and thethreshold voltage of the first transistor; V_(gtWi) is the first gateoverdrive; G_(m)** is a value of a Y intercept that is obtained byextrapolating the characteristic curve; f is the slope of thecharacteristic curve at the virtual point; G_(m)* is a Y coordinatevalue at the virtual point; and a prime is the first-orderdifferentiation of V_(gtWi).

According to a sixth aspect, the characteristic evaluation apparatus ofthe second aspect is characterized in that the threshold voltagedetermination means determines the optimum second to fourth estimatedvalues from a relational expression:${F\left( {\delta,V_{gtWi}} \right)} = {\frac{G_{m}^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}{f^{\prime}\left( {\delta,V_{gtWi}} \right)} + {{DW}^{*}\left( {\delta,V_{gtWi}} \right)}}$

where δ is a difference between an estimated value of the thresholdvoltage of the second transistor, i.e., a first estimated value, and thethreshold voltage of the first transistor; V_(gtWi) is the first gateoverdrive; G_(m)** is a value of a Y intercept that is obtained byextrapolating the characteristic curve; f is the slope of thecharacteristic curve at the virtual point; DW* is an X coordinate valueat the virtual point; and a prime is the first-order differentiation ofV_(gtWi).

According to a seventh aspect, a characteristic evaluation apparatus forinsulated gate type transistors in which at least two insulated gatetype transistors that differ from each other only in mask channel widthare used for evaluation and the characteristic of a first insulated gatetype transistor having a wide mask channel width serves as a reference,to evaluate the characteristic of a second insulated gate typetransistor having a narrow mask channel width. This apparatus comprises:a threshold voltage estimation means that extracts the threshold voltageof the first transistor, estimates the threshold voltage of the secondtransistor, and employs a value as estimated, as a first estimatedvalue; an extraction means in which (i) a difference between a gatevoltage of the first transistor and the threshold voltage of the firsttransistor is defined as a first gate overdrive, and a differencebetween a gate voltage of the second transistor and the first estimatedvalue is defined as a second gate overdrive, (ii) in an X-Y plane whoseX-axis is the mask channel width and Y-axis is source-drain conductance,a virtual point at which a change in Y coordinate value is estimated tobe approximately zero when the first and second gate overdrives arefinely changed from a first characteristic curve exhibiting arelationship between the mask channel widths of the first and secondtransistors and the source-drain conductance, and (iii) a value of the Xcoordinate at the virtual point is employed as a second estimated value,alternatively, as a value of the X intercept of the first characteristiccurve; a threshold voltage determination means in which (i) from thesecond estimated value, an optimum first estimated value is found withwhich a second characteristic curve exhibiting a relationship betweenthe second gate overdrive and the second estimated value in an X-Y planewhose X-axis is the second gate overdrive and Y-axis is a value relatedto the second estimated value, has a predetermined shape within apredetermined range of the second gate overdrive, and (ii) the optimumfirst estimated value is determined as a true threshold voltage of thesecond transistor; and a channel narrowing determination means thatdetermines a difference between the mask channel width and an effectivechannel width, based on the true threshold voltage.

According to an eighth aspect, the characteristic evaluation apparatusof the seventh aspect is characterized in that the extraction meansfurther employs a value of the X intercept of the first characteristiccurve as a third estimated value; and the threshold voltagedetermination means employs a value that is obtained by reducing thesecond estimated value from twice the third estimated value, as thevalue related to the second estimated value.

According to a ninth aspect, the characteristic evaluation apparatus ofthe eighth aspect is characterized in that the threshold voltagedetermination means employs the first estimated value with which a valuethat is obtained by reducing the second estimated value from twice thethird estimated value is best converged on a fixed value in thepredetermined range, as the optimum first estimated value.

According to a tenth aspect, the characteristic evaluation apparatus ofthe first aspect is characterized in that the channel narrowingdetermination means determines a difference between the mask channelwidth and an effective channel width, from a value that is obtained byreducing the second estimated value from twice the third estimated valuewhen the gate overdrive is in the vicinity of 0 V.

According to an eleventh aspect, a characteristic evaluation apparatusfor insulated gate type transistors in which at least two insulated gatetype transistors that differ from each other only in mask channel widthare used for evaluation and the characteristic of a first insulated gatetype transistor having a wide mask channel width serves as a reference,to evaluate the characteristic of a second insulated gate typetransistor having a narrow mask channel width. This apparatus comprises:a threshold voltage estimation means that extracts a threshold voltageof the first transistor, estimates the threshold voltage of the secondtransistor, and employs a value as estimated, as a first estimatedvalue; an extraction means in which (i) a difference between a gatevoltage of the first transistor and the extracted threshold voltage ofthe first transistor is defined as a first gate overdrive, and adifference between a gate voltage of the second transistor and the firstestimated value is defined as a second gate overdrive, (ii) under thecondition that the first and second gate overdrives are the same in anX-Y plane whose X-axis is the mask channel width and Y-axis issource-drain resistance, a virtual point at which a change in Ycoordinate value is estimated to be approximately zero even if the firstand second gate overdrives are finely changed, is extracted from pointson a straight line passing through a first point whose X coordinate isthe mask channel width of the first transistor and Y coordinate is thesource-drain resistance of the second transistor, and a second pointwhose X coordinate is the mask channel width of the second transistorand Y coordinate is the source-drain resistance of the first transistor,(iii) values of the X coordinate and Y coordinate at the virtual pointsare defined as second and third estimated values, respectively, and (iv)a slope of the straight line at the virtual points is extracted and avalue of the slope is employed as a fourth estimated value; a thresholdvoltage determination means that determines a true threshold voltage ofthe second transistor by using the first to fourth estimated values; anda channel narrowing determination means that determines a differencebetween the mask channel width and an effective channel width, based onthe true threshold voltage.

According to a twelfth aspect, in the characteristic evaluationapparatus of the eleventh aspect the threshold voltage determinationmeans is characterized in: (i) finding, from the second to fourthestimated values, optimum second to fourth estimated values with which achange of the third estimated value is equal to the product of a changeof the second estimated value and the fourth estimated value, in replyto fine changes of the first and second gate overdrives, (ii)determining an optimum first estimated value that corresponds to theoptimum second to fourth estimated values, and (iii) determining thetrue threshold voltage of the second transistor, based on the optimumfirst estimated value.

According to a thirteenth aspect, the characteristic evaluationapparatus of the twelfth aspect is characterized in that the thresholdvoltage determination means determines the optimum second to fourthestimated values from a relational expression:${F\left( {\delta,V_{gtWi}} \right)} = {{\frac{h^{2}\left( {\delta,V_{gtWi}} \right)}{h^{\prime}\left( {\delta,V_{gtWi}} \right)} \cdot {{dW}^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}} - {R^{\#}\left( {\delta,V_{gtWi}} \right)}}$

where δ is a difference between an estimated value of the thresholdvoltage of the second transistor, i.e., a first estimated value, and thethreshold voltage of the first transistor; V_(gtWi) is the first gateoverdrive; dW** is a value of an X intercept that is obtained byextrapolating the straight line; h is the slope of the straight line;R^(#) is a Y coordinate value at the virtual point; and a prime is thefirst-order differentiation of V_(gtWi).

According to a fourteenth aspect, the characteristic evaluationapparatus of the twelfth aspect is characterized in that the thresholdvoltage determination means determines the optimum second to fourthestimated values from a relational expression:${F\left( {\delta,V_{gtWi}} \right)} = {{R^{**}\left( {\delta,V_{gtWi}} \right)} - {\frac{h\left( {\delta,V_{gtWi}} \right)}{h^{\prime}\left( {\delta,V_{gtWi}} \right)} \cdot {R^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}} - {R^{\#}\left( {\delta,V_{gtWi}} \right)}}$

where δ is a difference between an estimated value of the thresholdvoltage of the second transistor, i.e., a first estimated value, and thethreshold voltage of the first transistor; V_(gtWi) is the first gateoverdrive; R** is a value of a Y intercept that is obtained byextrapolating the straight line; h is the slope of the straight line;R^(#) is a Y coordinate value at the virtual point; and a prime is thefirst-order differentiation of V_(gtWi).

According to a fifteenth aspect, the characteristic evaluation apparatusof the twelfth aspect is characterized in that the threshold voltagedetermination means determines the optimum second to fourth estimatedvalues from a relational expression:${F\left( {\delta,V_{gtWi}} \right)} = {\frac{R^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}{h^{\prime}\left( {\delta,V_{gtWi}} \right)} + {{DW}^{\#}\left( {\delta,V_{gtWi}} \right)}}$

where δ is a difference between an estimated value of the thresholdvoltage of the second transistor, i.e., a first estimated value, and thethreshold voltage of the first transistor; V_(gtWi) is the first gateoverdrive; R** is a value of a Y intercept that is obtained byextrapolating the straight line; h is the slope of the straight line;DW^(#) is an X coordinate value at the virtual point; and a prime is thefirst-order differentiation of V_(gtWi).

According to a sixteenth aspect, the characteristic evaluation apparatusof the twelfth aspect is characterized in that the threshold voltagedetermination means determines the optimum second to fourth estimatedvalues from a relational expression:${F\left( {\delta,V_{gtWi}} \right)} = {{{dW}^{**}\left( {\delta,V_{gtWi}} \right)} + {\frac{h\left( {\delta,V_{gtWi}} \right)}{h^{\prime}\left( {\delta,V_{gtWi}} \right)} \cdot {{dW}^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}} - {{DW}^{\#}\left( {\delta,V_{gtWi}} \right)}}$

where δ is a difference between an estimated value of the thresholdvoltage of the second transistor, i.e., a first estimated value, and thethreshold voltage of the first transistor; V_(gtWi) is the first gateoverdrive; dW** is a value of an X intercept that is obtained byextrapolating the straight line; h is the slope of the straight line;DW^(#) is an X coordinate value at the virtual point; and a prime is afirst-order differentiation of V_(gtWi).

According to a seventeenth aspect, in the characteristic evaluationapparatus of the eleventh aspect the threshold voltage determinationmeans is characterized in (i) finding, in an X-Y plane whose X-axis isthe second gate overdrive and Y-axis is the second estimated value, theoptimum first estimated value with which a characteristic curveexhibiting the relationship between the second gate overdrive and thesecond estimated value has a predetermined shape in a predeterminedrange of the second gate overdrive, and (ii) determining the truethreshold voltage of the second transistor, based on the optimum firstestimated value.

According to an eighteenth aspect, the characteristic evaluationapparatus of the seventeenth aspect is characterized in that thethreshold voltage determination means estimates, from the characteristiccurve in plural, an optimum characteristic curve with which the secondestimated value is best converged on a fixed value in the predeterminedrange.

According to a nineteenth aspect, the characteristic evaluationapparatus of the eleventh aspect is characterized in that the channelnarrowing determination means determines a difference between the maskchannel width and an effective channel width, from the second estimatedvalue when the gate overdrive is in the vicinity of 0 V.

The characteristic evaluation apparatus of the first or twelfth aspectallows accurate extraction of the threshold voltage of the secondinsulated gate type transistor, irrespective of the range of the secondgate overdrive, thereby improving the accuracy of effective channelwidth extraction.

The characteristic evaluation apparatus of the eleventh aspectfacilitates to determine the value of channel narrowing when the firstand second gate overdrives are in the vicinity of zero because thestationary point of the second estimated value is present in thevicinity of zero.

The characteristic evaluation apparatus of the second aspect facilitatesthe slope extraction between virtual points because a characteristiccurve is approximated to a straight line. This allows to find a virtualpoint as the intersection of straight lines, and the slope at anintersection as the slope of a straight line.

The characteristic evaluation apparatus of the third, fourth, fifth,sixth, thirteenth, fourteenth, fifteenth or sixteenth aspect requires nodifferentiation of the gate overdrive at a virtual point, therebyreducing errors.

The characteristic evaluation apparatus of the seventh, eighth orseventeenth aspect facilitates to determine true threshold voltagesbecause the second characteristic curves that are obtained for the truethreshold voltage on a graph may approximately coincide, irrespective ofmask channel width.

The characteristic evaluation apparatus of the ninth or eighteenthaspect facilitates programming for appropriate results by detecting anoptimum characteristic curve exhibiting the best convergence on a fixedvalue.

The characteristic evaluation apparatus of the tenth or nineteenthaspect facilitates channel narrowing determination because the channelnarrowing at the gate overdrive of 0 V is determined by using a valuethat is obtained by reducing the second estimated value from twice thethird estimated value, alternatively, because the second estimated valuehas a stationary point when the gate overdrive is in the vicinity of 0V.

To solve the above problem, it is an object of the present invention toobtain a characteristic evaluation apparatus for insulating gate typetransistors which performs evaluation of insulated gate type transistorsby using a characteristic evaluation method for insulated gate typetransistors which reduces the error due to the uncertainty of athreshold voltage to permit channel narrowing extraction of highaccuracy.

It is another object of the present invention to obtain a computerreadable storing medium that stores a characteristic evaluation program.

It is another object of the present invention to obtain a manufacturingmethod by which insulated gate type transistors having excellentcharacteristics can be manufactured easily by using the abovecharacteristic evaluation method.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graph for explaining an effective channel length extractionby Chia method;

FIG. 2 is a graph for explaining threshold voltage extraction;

FIG. 3 is a graph for explaining a virtual point, G_(m) intercept andW_(m) intercept in Gm method;

FIG. 4 is a flowchart giving an example of the procedure of acharacteristic evaluation method for insulated gate type transistorsaccording to a first preferred embodiment of the present invention;

FIG. 5 is a graph for explaining a true shift amount determinationaccording to the first preferred embodiment;

FIG. 6 is a graph for explaining the relationship between channelnarrowing and W_(m) coordinate at a virtual point;

FIG. 7 is a diagram for explaining a higher-order narrowing;

FIG. 8 is a block diagram giving an example of the construction of acharacteristic evaluation apparatus for insulated gate type transistorsaccording to the first preferred embodiment;

FIG. 9 is a conceptual diagram showing the concept in which acalculation section in FIG. 8 is implemented by a computer;

FIG. 10 is a flowchart showing the manufacturing steps for insulatedgate type transistors which employs the characteristic evaluation methodof the first preferred embodiment;

FIG. 11 is a graph showing the relationship between mask channel lengthand effective channel length in manufacturing an insulated gate typetransistor;

FIG. 12 is a graph showing the relationship between effective channellength and threshold voltage in manufacturing an insulated gate typetransistor;

FIG. 13 is a graph for explaining the outline of a second preferredembodiment of the present invention;

FIG. 14 is a graph showing the relationship between W_(m) coordinate ata virtual point and threshold voltage error;

FIG. 15 is a graph for explaining the relationship between W_(m)intercept and threshold voltage error;

FIG. 16 is a graph for explaining the relationship between a value thatis obtained by reducing the value of W_(m) coordinate at a virtual pointfrom twice the value of W_(m) intercept, and threshold voltage error;

FIG. 17 is a flowchart giving an example of the procedure of acharacteristic evaluation method for insulated gate type transistorsaccording to the second preferred embodiment;

FIG. 18 is a block diagram giving an example of the construction of acharacteristic evaluation apparatus for insulated gate type transistorsaccording to the second preferred embodiment;

FIG. 19 is a graph for explaining a virtual point, R intercept and W_(m)intercept in Rm method;

FIG. 20 is a flowchart giving an example of the procedure of acharacteristic evaluation method for insulated gate type transistorsaccording to a third preferred embodiment;

FIG. 21 is a graph for explaining a true shift amount determinationaccording to the third preferred embodiment;

FIG. 22 is a graph for explaining the relationship between channelnarrowing and W_(m) coordinate at a virtual point;

FIG. 23 is a block diagram giving an example of the construction of acharacteristic evaluation apparatus for insulated gate type transistorsaccording to the third preferred embodiment;

FIG. 24 is a graph for explaining the outline of a fourth preferredembodiment;

FIG. 25 is a graph showing the relationship between W_(m) coordinate ata virtual point and threshold voltage error;

FIG. 26 is a flowchart giving an example of the procedure of acharacteristic evaluation method for insulated gate type transistorsaccording to the fourth preferred embodiment;

FIG. 27 is a block diagram giving an example of the construction of acharacteristic evaluation apparatus for insulated gate type transistorsaccording to the fourth preferred embodiment;

FIG. 28 is a graph for explaining the difference between the channelnarrowing obtained by prior art characteristic evaluation method and thechannel narrowing obtained by the characteristic evaluation method ofthe first or third preferred embodiment; and

FIG. 29 is a graph showing the relationship between gate overdrive areaset for calculation in the characteristic evaluation method of the firstor third preferred embodiment, and channel narrowing.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Preferred Embodiment

A characteristic evaluation method for insulated gate type transistorsaccording to a first preferred embodiment will be described hereafter.In this method, a channel narrowing DW is extracted by using the draincurrent in the linear areas of a plurality of transistors, each havingthe same mask channel length L_(m) and a different mask channel widthW_(m).

The above characteristic evaluation method will be roughed out. Firstlythere are prepared at least two MOS transistors, each having the samechannel length L_(m) and a different mask channel width W_(m). In thefollowing description, the number of MOS transistors is limited to two.Of the two MOS transistors, one having a wide mask channel width W_(m)is referred to as a wide transistor or first insulated gate typetransistor, and the other having a narrow mask channel width W_(m) isreferred to as a narrow transistor or second insulated gate typetransistor. Subscript Wi in symbols stands for being concerned with thewide transistor, and subscript Na stands for being concerned with thenarrow transistor. In the prior art method that is described byreferring to FIG. 2, the threshold voltages V_(thWi), V_(thNa) of thewide transistor and narrow transistor, respectively, are extrapolatedfrom I_(ds)−V_(gs) characteristic or the like. The threshold voltageV_(thNa) of the second insulated gate type transistor thus obtained is afirst estimated value. By changing the threshold voltage V_(thNa) of thenarrow transistor (the first estimated value) with the threshold voltageV_(thWi) of the wide transistor fixed, a coordinate (DW*, G_(m)*) at avirtual point at which the change in source-drain conductance isestimated to be approximately zero even if a gate overdrive V_(gt) isfinely changed against each of the changed threshold voltage V_(thNa),is extracted from, for example, the intersection coordinates of aplurality of characteristic curves having a different gate overdriveV_(gt). In this case, the gate overdrive V_(gt) of the wide transistoris a first gate overdrive, and the gate overdrive V_(gt) of the narrowtransistor is a second gate overdrive. The coordinate DW*, coordinateG_(m)* and slope f at the virtual point are second, third and fourthestimated values, respectively.

Then, by using the threshold voltages V_(thWi) and V_(thNa), thecoordinate (DW*, G_(m)*) at the virtual point is extracted from therelationship between conductance G_(m) and mask channel width W_(m).Examples of this method is, as shown in FIG. 3 in prior art, one inwhich two characteristic curves (straight lines) representing thecharacteristic G_(m)−W_(m) are drawn in a graph whose X-axis is maskchannel width W_(m) and Y-axis is source-drain conductance G_(m), andthe intersection of the two straight lines is found to extract a virtualpoint. In FIG. 3, the straight line expressing the gate overdrive V_(gt)is a first straight line, the point that satisfies the mask channelwidth W_(m)=W_(mWi) on the first straight line is a first point, and thepoint that satisfies the mask channel width W_(m)=W_(mNa) on the firststraight line is a second point. However, the estimation of thecoordinate at a virtual point is not limited to the above. Instead of astraight line passing through two points, a curve to be determined bythree or more points may be used. Alternatively, a point in the vicinityof an intersection may be used instead of the intersection. From amongthe values of a coordinate (DW*, G_(m)*) which express the extractedvirtual point, there is determined the value with which the change inthe value G_(m) of the Y component of the coordinate expressing avirtual point is estimated to be equal to the product of the change ofthe value DW* of the X component of the virtual point and the channelresistance value f per unit width.

Extraction of an effective channel width W_(eff) in MOS transistors willbe described in detail by referring to FIG. 4.

Firstly, the I_(ds)−V_(gs) characteristics of two transistors Wi and Na,each having the same mask channel length L_(m) and a different maskchannel width W_(m), are measured (step ST1.1).

From the obtained I_(ds)−V_(gs) characteristics, the threshold voltagesV_(thWi) of a wide transistor and V_(thNa) of a narrow transistor areextracted by using extrapolation method or the like (step ST1.2). Then,the difference (V_(thNa)−V_(thWi)) between the threshold voltagesV_(thWi) and V_(thNa) is found. Hereafter, the difference(V_(thNa)−V_(thWi)) thus found is defined as δ_(guess).

The lower and upper limits of an area in which the value δ to be set asa threshold voltage difference is changed are determined asδ_(inf)=δ_(guess)−K and δ_(sup)=δ_(guess)+K, respectively (step ST1.3).Here, let K be 0.2 V, and δ=δ_(inf) is set as an initial value.

Then, it is determined whether the value δ to be calculated is presentbetween δ_(inf) and δ_(sup) (step ST1.4). That is, it is determinedwhether δ_(inf)≦δ≦δ_(sup).

When the value δ is present between δ_(inf) and δ_(sup), the thresholdvoltage V_(thWi) of the wide transistor is fixed to the value that hasbeen extracted in step ST1.2, and the threshold voltage V_(thNa) of thenarrow transistor is supposed to be the sum of the threshold voltageV_(thWi) of the wide transistor and the δ (step ST1.5).

On the basis of the threshold voltage V_(thWi) and V_(thWi)+δ in stepST1.5, a gate overdrive V_(gt) is measured. For about 20 points in acertain area Ω, e.g., in the range of the gate overdrive V_(gt)satisfying 0.3 V≦V_(gt)≦1.3 V, there are found the rate of changeDW*′(δ, V_(gtn)) in the value of W_(m) coordinate at a virtual point,the rate of change G_(m)*′(δ, V_(gtn)) in the value of G_(m) coordinateat a virtual point, and the conductance f (δ, V_(gtn)) per unit width.From the values thus found, the value of function F(δ, V_(gtn))expressed by Equation 6 is found:

 F(δ, V _(gtn))=G _(m) *′−f·DW*′ where n=1, 2, . . . 20.  (Eq. 6)

Next, the standard deviation of function F, σ[F(δ)], is calculated inthe area Ω (step ST1.7). By substituting δ+Q for δ, the value of a shiftamount δ is changed to return to step ST1.4 (step ST1.8). Let the valueof Q be 0.01, for example.

When it is determined δ_(inf)≦δ≦δ_(sup) in step ST1.4, steps ST1.5 toST1.8 are repeated. On the other hand, when it is not determinedδ_(inf)≦δ≦δ_(sup) in step ST1.4, it goes to step ST1.9 and find δ=δ₀,with which the standard deviation σ[F(δ)] becomes a minimum. At thattime, the true threshold voltage V_(thNa) of the narrow transistor isgiven by the sum of the threshold voltage V_(thWi) of the widetransistor and the δ₀ that has been determined in step ST1.9.

Using the true threshold voltage V_(thWi)+δ₀ of the narrow transistorthat has been determined in step ST1.9, the gate overdrive V_(gt) of thenarrow transistor is measured to find the value DW*(V_(gt)) of W_(m)coordinate at a virtual point (step ST1.10). The threshold voltageV_(thWi) of the wide transistor at that time is based on the value thathas been found in step ST1.2, as in step ST1.5.

Let the channel narrowing DW_(Na) of the narrow transistor beDW_(Na)(V_(gt))=dW**(V_(gt)), where dW** is an optimum second estimatedvalue (step ST1.11). At the same time an effective channel widthW_(effNa) is given by the following Equation 7. Here at, G_(m)* that isobtained by using a gate overdrive V_(gt) providing a channel narrowingDW is an optimum third estimated value. Further, an optimum fourthestimated value is the conductance f of the channel per unit width whichis obtained by using a gate overdrive V_(gt) providing a channelnarrowing DW:

 W _(effNa)(V _(gt))=W _(mNa) −DW _(Na)(V _(gt))  (Eq.7)

Although in step ST1.11, the channel narrowing DW_(Na) is determinedfrom dW**, the channel narrowing DW(V_(gt)) when a gate overdrive V_(gt)is in the vicinity of zero may be determined as a value (2·dW**−DW*),which is given from W_(m) coordinate at an intersection and W_(m)intercept. In this case, when the gate overdrive V_(gt) is in thevicinity of zero, the change of (2·dW**−DW*) against the change of gateoverdrive V_(gt) is extremely small, thus making it easy to determine achannel narrowing DW_(Na).

Description will be now given of a concrete procedure to determine achannel narrowing DW and the like, from the standard deviation of thefunction F shown in Equation 6. In a characteristic evaluation methodfor insulated gate type transistors according to the first preferredembodiment, to reduce the uncertainty of threshold voltage extrapolationand, in particular, the error due to the uncertainty of thresholdvoltage extrapolation for transistors having a narrow channel width, therelationship of Equation 8 which is, for example, established betweenthe value DW* of W_(m) coordinate at a virtual point and the value dW**,is noted to apply a variation method. Here, dW** is the value of Xintercept that is obtained by extrapolating a G_(m)−W_(m) characteristiccurve (straight line) which is plotted between source-drain conductanceG_(m) and mask channel width W_(m), by using G_(m) to enter a Y-axis andW_(m) to enter an X-axis. Hereinafter, dW** may be taken to representthe value of W_(m) intercept. $\begin{matrix}{{{dW}^{**} + {\frac{f}{f^{\prime}}{dW}^{**^{\prime}}} - {DW}^{*}} = 0} & \left( {{Eq}.\quad 8} \right)\end{matrix}$

Supposing that the threshold voltage difference between the narrowtransistor and the wide transistor is a shift amount δ, the value DW* ofW_(m) coordinate at a virtual point, the value dW** of W_(m) interceptand its rate of change dW**′, as well as the channel conductance f perunit width and its rate of change f′, are found fromG_(mNa)(V_(gtWi)+δ−V_(thNa)+V_(thWi)) and G_(mWi)(V_(gtWi)). When ashift amount δ is equal to the true threshold voltage difference δ₀between the narrow transistor and the wide transistor, Equation 8 issatisfied. At that time, dW** gives a channel narrowing DW. Therefore, achannel narrowing DW can be extracted through the following procedure.

Firstly, with respect to a certain shift amount δ, the value DW* ofW_(m) coordinate at a virtual point, the value dW** of W_(m) intercept,and the channel conductance f per unit width are given by Equations 9 to11: $\begin{matrix}{\quad {{DW}^{*} = \frac{W_{mNa} - {{ri} \cdot W_{mWi}}}{\left( {1 - {ri}} \right)}}} & \left( {{Eq}.\quad 9} \right) \\{\quad {{dW}^{**} = \frac{W_{mNa} - {{rai} \cdot W_{mWi}}}{\left( {1 - {rai}} \right)}}} & \left( {{Eq}.\quad 10} \right) \\{{f\left( {V_{gtWi},\delta} \right)} = \frac{{G_{mWi}\left( V_{gtWi} \right)} - {G_{mNa}\left( {V_{thWi} + \delta - V_{gtNa} + V_{thWi}} \right)}}{W_{mWi} - W_{mNa}}} & \left( {{Eq}.\quad 11} \right)\end{matrix}$

In Equations 9 to 11, parameters ri and rai are defined by the followingEquations 12 and 13, respectively, and V_(gtWi) denotes a gate overdriveon the basis of the threshold voltage V_(thWi) of a wide transistorhaving a wide mask channel width W_(mWi): $\begin{matrix}{{{ri}\left( {V_{gtwi},\delta} \right)} \equiv \frac{{G_{mNa}}^{\prime}\left( {V_{gtWi} + \delta - V_{thNa} + V_{thWi}} \right)}{{G_{mWi}}^{\prime}\left( V_{gtWi} \right)}} & \left( {{Eq}.\quad 12} \right)\end{matrix}$

$\begin{matrix}{{{rai}\left( {V_{gtwi},\delta} \right)} \equiv \frac{G_{mNa}\left( {V_{gtwi} + \delta - V_{thNa} + V_{thWi}} \right)}{G_{mWi}\left( V_{gtWi} \right)}} & \left( {{Eq}.\quad 13} \right)\end{matrix}$

The value DW* of W_(m) coordinate at a virtual point, the value dW** ofW_(m) intercept and its rate of change dW**′, as well as the channelconductance f per unit width and its rate of change f′, are found bychanging a shift amount δ.

The function F in Equation 6 can be modified to redefine as thefollowing Equation 14, making it easy to find the function F. When ashift amount δ is equal to a threshold voltage difference δ₀ between thenarrow transistor and the wide transistor, the function F defined inEquation 14 becomes zero, irrespective of a gate overdrive V_(gtWi).Then, a shift amount δ with which the standard deviation of function Fin an area of gate overdrive V_(gtWi) becomes a minimum, is determinedas a true threshold voltage difference δ₀: $\begin{matrix}{{F\left( {V_{gtWi},\delta} \right)} = {{{dW}^{**}\left( {V_{gtWi},\delta} \right)} + {\frac{f\left( {V_{gtWi},\delta} \right)}{f^{\prime}\left( {V_{gtWi},\delta} \right)} \cdot {{dW}^{**^{\prime}}\left( {V_{gtWi},\delta} \right)}} - {{DW}^{*}\left( {V_{gtWi},\delta} \right)}}} & \left( {{Eq}.\quad 14} \right)\end{matrix}$

FIG. 5 is a graph showing one example of the relationship between thestandard deviation of function F and shift amount δ. In this graph, aminimum value is obtained when the shift amount δ is −0.06 V, thus let atrue threshold voltage difference δ₀ be −0.06 V.

The value of a channel narrowing DW is determined by using the value ofthe above threshold voltage difference δ₀. For instance, it may bedetermined in the same manner as in step ST1.11 of FIG. 4.Alternatively, the average of values obtained when the gate overdriveV_(gt) is in the vicinity of zero, among the values DW* (δ₀, V_(gt)) ofW_(m) coordinate at a virtual point, may be taken as the value of achannel narrowing DW. FIG. 6 gives an example of the results when thecharacteristic evaluation method of MOS transistors according to thefirst preferred embodiment (hereinafter referred to as Gm method) isapplied to a process.

Instead of Equation 14 that is used in the first preferred embodiment,any one of Equations 15 to 17 may be used to find function F:$\begin{matrix}{{F\left( {\delta,V_{gtWi}} \right)} = {{\frac{f^{2}\left( {\delta,V_{gtWi}} \right)}{f^{\prime}\left( {\delta,V_{gtWi}} \right)} \cdot {{dW}^{**}\left( {\delta,V_{gtWi}} \right)}} - {G_{m}^{*}\left( {\delta,V_{gtWi}} \right)}}} & \left( {{Eq}.\quad 15} \right) \\{{F\left( {\delta,V_{gtWi}} \right)} = {{G_{m}^{**}\left( {\delta,V_{gtWi}} \right)} - {\frac{f\left( {\delta,V_{gtWi}} \right)}{f^{\prime}\left( {\delta,V_{gtWi}} \right)} \cdot {G_{m}^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}} - {G_{m}^{*}\left( {\delta,V_{gtWi}} \right)}}} & \left( {{Eq}.\quad 16} \right) \\{\quad {{F\left( {\delta,V_{gtWi}} \right)} = {\frac{G_{m}^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}{f^{\prime}\left( {\delta,V_{gtWi}} \right)} + {{DW}^{*}\left( {\delta,V_{gtWi}} \right)}}}} & \left( {{Eq}.\quad 17} \right)\end{matrix}$

In Equations 16 and 17, G_(m)** is the value of a R intercept that isobtained by extrapolating G_(m)−W_(m) characteristic. Thus, by usingmask channel width W_(m) to enter the X-axis and source-drainconductance G_(m) to enter the Y-axis, without using any coordinate at avirtual point, a G_(m)−W_(m) characteristic curve (straight line) isextrapolated to obtain the value G_(m)** of a Y intercept and the valuedW** of a Y intercept which are found as X=0 and Y=0, respectively. Theuse of the value G_(m)** or dW** requires no differentiation of thecoordinate (DW*, R*) at a virtual point. The accuracy is unchanged byusing any one of Equations 14 to 17. Equation 15 and 16, however, callfor calculation of G_(m)**. Hence, Equation 14 or 17 is preferred.

Although in the first preferred embodiment, a shift amount δ isdetermined by a value with which the standard deviation of function Fbecomes a minimum, it can be determined by a value with which theaverage value of functions F approaches zero, or the minimum value ofthe sum of squares (ΣF²) of function F. The above alternatives, however,might have the errors due to the offset of the value of function F,which are caused by calculation errors, unlike the value with which thestandard deviation becomes a minimum.

Moreover, the first preferred embodiment employs G_(mNa)′/G_(mWi)′ inEquation 12, for example, to improve calculation accuracy in finding thevalue DW* of W_(m) coordinate at a virtual point. On the other hand, ifeasy process is desired, a higher accuracy calculation than prior art isattainable by using δG_(mNa)/δG_(mWi), instead of G_(mNa)′/G_(mWi)′.High-accuracy channel narrowing DW extraction is also attainable byhigh-accuracy calculation of the change in the source-drain conductanceG_(m) of a wide transistor or narrow transistor, by means of ahigher-order approximate expression. For instance, the slope of a curveat y₀ among points that are equally spaced with a width s, as shown inFIG. 7, can be given by a higher-order approximate expression in thefollowing Equation 18: $\begin{matrix}{y_{0}^{\prime} = {\frac{1}{12 \cdot h}\left( {y_{- 2} - {8 \cdot y_{- 1}} + {8 \cdot y_{1}} - y_{2}} \right)}} & \left( {{Eq}.\quad 18} \right)\end{matrix}$

The use of the characteristic evaluation method for insulated gate typetransistors in the first preferred embodiment permits evaluation athigher accuracy than prior art. As a result, improvement of accuracyowing to use of G_(mNa)′/G_(mWi)′ is satisfactorily reflected onevaluation results than prior art.

In the calculation of G_(mNa)′/G_(mWi)′ by Gm method, to reduce errors,resistance R is sometimes used instead of conductance G_(m), as shown inEquation 19. The reason for using the differentiation of the logarithmof resistance R is to reduce the error due to a great change inresistance R when V_(gt) is brought near zero: $\begin{matrix}{\frac{G_{mNa}^{\prime}}{G_{mWi}^{\prime}} = {\frac{\left( {1/R_{Na}} \right)^{\prime}}{\left( {1/R_{Wi}} \right)^{\prime}} = {{\frac{R_{Na}^{\prime}}{R_{Wi}^{\prime}} \cdot \frac{R_{Wi}^{2}}{R_{Na}^{2}}} = {\frac{\left( {lnR}_{Na} \right)^{\prime}}{\left( {lnR}_{Wi} \right)^{\prime}} \cdot \frac{R_{Wi}}{R_{Na}}}}}} & \left( {{Eq}.\quad 19} \right)\end{matrix}$

Description will be now given of a characteristic evaluation apparatusfor insulated gate type transistors according to the first preferredembodiment, by referring to FIG. 8. A characteristic evaluationapparatus for insulated gate type transistors 1 is connected to ameasuring device 3 for measuring an object under test 2. Examples of theobject under test 2 are integrated circuits in which a wide transistorand a narrow transistor are formed. Such an integrated circuit afterbeing extracted from the lot for which all manufacturing steps have beenterminated, is set to the measuring device 3 to make measurementtherefor. The measuring device 3 is controlled by a control section 4 ofthe characteristic evaluation apparatus 1. An input section 5 providesthe control section 4 with control information. The input section 5 iscomposed of a keyboard, a mouse and the like. Measurement data obtainedin the measuring device 3 is inputted to a calculation section 6together with the control information, through the control section 4.The calculation section 6 extracts an effective channel width W_(eff),based on the data to be inputted from the input section 5. An outputsection 7 outputs the extracted effective channel width W_(eff) and thecontrol information used in the middle of extraction. Such controlinformation is provided from the control section 4 or calculationsection 5.

The calculation section 6 is composed of a threshold voltage and virtualshift amount determination section 11 that determines threshold voltagesV_(thWi), V_(thNa), and virtual shift amount δ; an extraction section 12that extracts an intersection coordinate (DW*, G_(m)*) as the coordinateat a virtual point, and the slope f of a characteristic curve at theintersection coordinate; a true shift amount determination section 13for determining a true shift amount δ₀, and a channel narrowingdetermination section 14 for determining channel narrowing DW (or aneffective channel width W_(eff)). Although in this embodiment, anintersection coordinate is used as the coordinate at a virtual point atwhich the change of source-drain conductance G_(m) is supposed to beapproximately zero even if the gate overdrive V_(gt) is finely changedin a W_(m)−G_(m) characteristic curve. The intersection coordinate maybe found by other than the method of finding an intersection,alternatively, other point may be used as the coordinate at a virtualpoint, as previously discussed. For executing calculation in thecalculation section 6, the value of a variable K for determining theupper limit δ_(sup) and lower limit δ_(inf) in the range of changing ashift amount δ, the range of area Ω in which a gate overdrive V_(gt) ismeasured, and the quantity of change Q of a virtual shift amount δ, areinputted to the threshold voltage and virtual shift amount determinationsection 11 from the input section 5. The measurement data ofsource-drain current I_(ds) and gate-source voltage V_(gt) are providedto the threshold voltage and virtual shift amount determination section11, from the control section 4. The determination section 11 receivesthe above data, and then provides the extraction section 12 with thethreshold voltage V_(thWi) of a wide transistor and a virtual shiftamount δ that indicates the difference between this threshold voltageV_(thWi) and the threshold voltage V_(thNa) of a narrow transistor. Inthe extraction section 12, with respect to each shift amount δ, the rateof change dDW*/dV_(gt) and that of dG_(m)/dV_(gt) for an intersectioncoordinate (DW*, G_(m)*) in an area Ω, and the slope f of acharacteristic curve are extracted by using the value of the maskchannel width W_(m) provided from the input section 5, as well as thesource-drain current I_(ds) and the measurement data of gate-sourcevoltage V_(gt). From the rate of change dDW*/dV_(gt) of W_(m) coordinateof the intersection, the rate of change dG_(m)/dV_(gt) of R coordinateof the intersection, and the slope f of the characteristic curve whichhave been extracted in the extraction section 12, the true shift amountdetermination section 13 determines a virtual shift amount δ₀ with whichthe standard deviation of the function F expressed in Equation 6 becomesa minimum in an area Ω. Upon determination of a virtual shift amount δ₀,the extraction section 12 outputs the virtual shift amount δ₀ and thevalue DW* of W_(m) coordinate of the corresponding intersection or thevalue dW** of W_(m) intercept, to a channel narrowing determinationsection 14. In the section 14, a channel narrowing DW is determined fromthe value dW** of W_(m) intercept or the value DW* of W_(m) coordinateat a virtual point, and the calculation expressed in Equation 7 iscarried out to determine an effective channel width W_(eff). The outputsection 7 outputs the channel narrowing DW and the effective channelwidth W_(eff) determined in the channel narrowing determination section14, the intersection coordinate (DW*, G_(m)*) and the slope of acharacteristic curve at the intersection coordinate extracted in theextraction section 12, and the true shift amount δ₀ determined in thetrue shift amount determination section 13.

With the above construction, it is possible to obtain a characteristicevaluation apparatus for insulated gate type transistors which extractsan effective channel width W_(eff) at a higher accuracy than prior art.

Referring to FIG. 9, the characteristic evaluation for insulated gatetype transistors as described in the first preferred embodiment can berealized by making a computer to read an evaluation program 30 forevaluating insulated gate type transistors from a recording mediumstoring the program 30, in accordance with the procedure in FIG. 4 asdescribed in the first preferred embodiment. By executing the evaluationprogram 30, a measurement data 33 containing data related to aneffective channel width W_(eff) can be extracted on the basis of ameasurement data 31 provided from a measuring device 3 and a controlinformation 32 from an input section 5 in FIG. 8, as described in thefirst preferred embodiment.

Description will be now given of a method of manufacturing an insulatedgate type transistor according to the first preferred embodiment, byreferring to FIG. 10. Firstly, a target narrow transistor and areference wide transistor are prepared (step ST50). Then, the electricalcharacteristics of both transistors are measured (step ST51). In thisstep, the I_(ds)−V_(gs) characteristic, off leak current I_(off) anddrain current I_(dmax) of each transistor are measured. The off leakcurrent I_(off) is the current that flows between source and drain when,for example, V_(ds)=VDD and V_(gs)=V_(bs)=0 V, where VDD is power supplyvoltage.

By the characteristic evaluation method for insulated gate typetransistors as described in the first preferred embodiment, thethreshold voltage V_(thNa) and effective channel width W_(effNa) of thenarrow transistor are extracted from I_(ds)−V_(gs) characteristic or thelike. Then, it is determined whether the threshold voltage V_(thNa),effective channel width W_(effNa), current I_(dmax), and current I_(off)of the narrow transistor satisfy a specification (step ST53). If not, itreturns to step ST50 to perform another preparation of transistors byusing a new mask.

Thus, the characteristic evaluation method for insulated gate typetransistors according to the first preferred embodiment produces thefollowing effects. Firstly, since the threshold voltage is determinedaccurately from a known mask channel width and electricalcharacteristics, the time required for manufacturing is reduced,compared to the case where the section of an insulated gate typetransistor is observed with an electron microscope or the like.Secondly, in response to a gate overdrive V_(gt), the range of aneffective channel width W_(eff) in the desired mask channel width W_(m)is found accurately (see FIG. 11). Thirdly, the variable range of thethreshold voltage V_(th) that corresponds to the variable range of aneffective channel width W_(eff) is found accurately at the same time(see FIG. 12), thus facilitating the quality control of the thresholdvoltage V_(th) in manufacturing steps.

Second Preferred Embodiment

Description will be given of the outline of a characteristic evaluationmethod for insulated gate type transistors according to a secondpreferred embodiment, by referring to FIG. 13. FIG. 13 is a graphshowing the relationship between the value of (2·dW**−DW*) and gateoverdrive V_(gt) which are obtained by the characteristic evaluationmethod for insulated gate type transistors according to the secondpreferred embodiment. Specifically, this graph shows the change in thevalue of (2·dW**−DW*) when a true threshold voltage is used for threenarrow transistors which differ one another in mask channel widthW_(mNa). Note that the mask channel width W_(mWi) of a wide transistorwhich serves as a reference in extracting the values dW** and DW* ofW_(m) coordinate of these narrow transistors, is set to the same value.A comparison of FIG. 13 with FIGS. 14 to 16 indicates that when used atrue threshold voltage, the change in the value of (2·dW**−DW*) againstthe gate overdrive V_(gt) is approximately the same, irrespective of themask channel widths W_(mNa) of the narrow transistors. Therefore, thetrue threshold voltage of a narrow transistor can be extracted byfinding out one which coincides with the characteristic curve of thisgraph when the value of a gate overdrive V_(gt) is, for example, in therange of 0.3-1.2 V. In the second preferred embodiment, first and secondinsulated gate type transistors, first and second gate overdrives, andfirst and second estimated values, are also defined as in the firstpreferred embodiment.

Description will be now given of an example of a characteristicevaluation method for insulated gate type transistors according to thesecond preferred embodiment. In this method, the characteristic curve ofFIG. 13 is extracted from characteristic curves that change variouslydepending on the estimated value of the threshold voltage V_(thNa) of anarrow transistor, namely, a first estimated value, by making use of thefact that the standard deviations of the characteristic curves are smallin the range of 0.2-0.6 V, for example. Since in this method the truethreshold voltage of a narrow transistor is determined by utilizing thedependence of (2·dW**−DW*) on a gate overdrive V_(gt), it is determinedin a procedure similar to that of the first preferred embodiment.

One example of the extraction procedure of an effective channel widthW_(eff) in the second preferred embodiment is given in FIG. 17. Theextraction procedure of the second preferred embodiment is differentfrom that of the first preferred embodiment in steps ST1.12, ST1.13 andST1.14 to ST1.16 in FIG. 17, which correspond to steps ST1.6, ST1.7 andST1.9 to ST1.11 in FIG. 4, respectively.

In step ST1.12, the value of 2·dW**−DW* against, for example, about 20different gate overdrives V_(gtn) are found by using the values of W_(m)coordinate and W_(m) intercept. In step ST1.13, there are calculated theaverage value <2·dW**−DW*> and standard deviation σ[2·dW**−DW*] of avalue that is obtained by reducing the value DW* of W_(m) coordinate ata virtual point from twice of the value dW** of W_(m) intercept for ashift amount δ.

When it is judged that in step ST1.13, the calculation of a shift amountδ in a predetermined range of δ_(inf) to δ_(sup) is terminated (stepST1.4), a true shift amount δ₀ that gives a channel narrowing DW isestimated in step ST1.14. The true shift amount δ₀ is a shift amount δ₀with which a standard deviation σ[2·dW**−DW*] becomes a minimum. Thismeans that the choice of a characteristic curve whose values are bestconverged on a fixed value. In step ST1.15, a channel narrowing DW isgiven by, for example, the average of the values DW* of W_(m) coordinateat a virtual point for a shift amount δ₀. In step ST1.16, an effectivechannel width W_(eff) is determined from the difference between a maskchannel width W_(m) and the channel narrowing DW.

Referring to FIG. 18, a characteristic evaluation apparatus forinsulated gate type transistors according to the second preferredembodiment will be described. A characteristic evaluation apparatus forinsulated gate type transistors 1A shown in FIG. 18 is connected to ameasuring device 3 for measuring an object under test 2, like thecharacteristic evaluation apparatus 1 of the first preferred embodimentas shown in FIG. 8. In the construction of the characteristic evaluationapparatus 1A, the same reference numerals have been retained for similarparts which have the same functions as in the apparatus 1 of FIG. 8.That is, the characteristic evaluation apparatus 1A has the samestructure as the apparatus 1, except for an extraction section 12A, atrue shift amount determination section 13A and a channel narrowingdetermination section 14A in a calculation section 6A. The extractionsection 12A finds (2·dW**−DW*) by changing a gate overdrive V_(gt) in anarea Ω. In the true shift amount determination section 13A, a value withwhich the standard deviation σ[2·dW**−DW*] becomes a minimum, is foundfrom the value DW* of W_(m) coordinate of an intersection and the valuedW* of W_(m) intercept in the area Ω, to determine a true shift amountδ₀. The extraction section 12A outputs the true shift amount δ₀ and thevalue DW* of W_(m) coordinate of the corresponding intersection or thevalue dW* of W_(m) intercept, to the channel narrowing determinationsection 14A. The section 14A determines a channel narrowing DW from theaverage of (2·dW**−DW*) when the gate overdrive V_(gt) is in thevicinity of 0 V, e.g., in the range of 0.2≦V_(gt)≦0.6, in an area Ω fora true shift amount δ₀, alternatively, from the value dW** of W_(m)intercept. In the second preferred embodiment, a value with which thestandard deviation σ[2·dW**−DW*] of the value (2·dW**−DW*) becomes aminimum, or a value with which the standard deviation σ[dW**] of thevalue dW** of W_(m) intercept becomes a minimum, is determined as achannel narrowing DW. Its determination method is, however, not limitedto the above, and the threshold voltage V_(thNa) of a narrow transistormay be determined by selecting a characteristic curve in which the valuedW** of W_(m) intercept or the value of (2·dW**−DW*) is best convergedon a fixed value when a gate overdrive V_(gt) is within a predeterminedrange.

A method of manufacturing an insulted gate type transistor according tothe second preferred embodiment can be implemented by employing, in stepST52 shown in FIG. 10, the evaluation method of the second preferredembodiment in place of that of the first preferred embodiment. Thisresults in the same effects as in the case where the evaluation methodof the first preferred embodiment is applied to a manufacturing method.

Referring again to FIG. 9, the characteristic evaluation for insulatedgate type transistors as described in the second preferred embodiment isattainable by making a computer to read an evaluation program 30 forevaluating insulated gate type transistors from a recording mediumstoring the program 30, in accordance with the procedure in FIG. 17 asdescribed in the second preferred embodiment.

In the channel narrowing DW extraction according to the first or secondpreferred embodiment, when the mask cannel width W_(mNa) of a narrowtransistor is significantly smaller than the mask cannel width W_(mWi)of a wide transistor (i.e., W_(mNa)<<W_(mWi)), the difference betweenthe mask channel width W_(mWi) and a gate finished width W_(gWi) hardlyaffects on determination of the value DW* of W_(m) coordinate at avirtual point, thereby determines the channel narrowing DW of the narrowtransistor at high accuracy. For instance, to evaluate device or circuitperformance on the level of not more than 1.0 μm in pattern width, it isrequired to extract the channel narrowing DW of each transistor. Forsuch an extraction, there are used two transistors, i.e., a narrowtransistor and a wide transistor serving as a reference. In this case,the difference between a gate finished width W_(g) and a mask channelwidth W_(m) depends on the transistor, causing an error. Thus,description will be now given of such an error. The value dW** of W_(m)coordinate at a virtual point when a mask channel width W_(m) is used isgiven by Equation 20: $\begin{matrix}{{{dW}^{**}\left( V_{gt} \right)} = {\left( {W_{mNa} - {\frac{G_{mNa}}{G_{mWi}} \cdot W_{mWi}}} \right) \cdot \left( {1 - \frac{G_{mNa}}{G_{mWi}}} \right)^{- 1}}} & \left( {{Eq}.\quad 20} \right)\end{matrix}$

If W_(g) intercept in a plane formed by gate finished width andsource-drain conductance (i.e., W_(g)−G_(m) plane), is represented bydW_(g)**, Equation 21 is obtained: $\begin{matrix}{{{dW}_{g}^{**}\left( V_{gt} \right)} = {\left( {W_{gNa} - {\frac{G_{mNa}}{G_{mWi}} \cdot W_{gWi}}} \right) \cdot \left( {1 - \frac{G_{mNa}}{G_{mWi}}} \right)^{- 1}}} & \left( {{Eq}.\quad 21} \right)\end{matrix}$

If the difference between a gate finished width W_(g) and a mask channelwidth W_(m) is represented by ΔW, the difference between the gatefinished width W_(gWi) and mask channel width W_(mWi) of a widetransistor, and the difference between the gate finished width W_(gNa)and mask channel width W_(mNa) of a narrow transistor are represented byΔW_(wi) and ΔW_(Na), respectively, thus the relationships of Equations22 and 23 are established. From Equations 20 to 23, the differencebetween the coordinate value dW** of W_(m) intercept and the coordinatevalue DW_(g)* of W_(g) intercept is expressed by Equation 24, where ΔWis defined in Equation 25:

W _(gWi) =W _(mWi) +ΔW _(Wi)  (Eq. 22)

W _(gNa) =W _(mNa) +ΔW _(Na)  (Eq. 23)

$\begin{matrix}\begin{matrix}{{{dW}^{**} - {dW}_{g}^{**}}\quad = {{{- \Delta}\quad W_{Na}} + {{\frac{G_{mNa}}{G_{mWi}} \cdot \left( {1 - \frac{G_{mNa}}{G_{mWi}}} \right)^{- 1} \cdot \Delta}\quad W}}} \\{\quad {\approx {{{- \Delta}\quad W_{Na}} + {{\frac{G_{mNa}}{G_{mWi}} \cdot \Delta}\quad W}}}} \\{\quad {\approx {{{- \Delta}\quad W_{Na}} + {{\frac{W_{effNa}}{W_{effWi}} \cdot \Delta}\quad W}}}}\end{matrix} & \left( {{Eq}.\quad 24} \right)\end{matrix}$

 ΔW=ΔW _(Wi) −ΔW _(Na)  (Eq. 25)

Equations 23 and 24 show that the effective channel width W_(eff) of anarrow transistor is extracted when the relationship W_(mNa)<<W_(mWi) isestablished. In Equation 24, the second term of the last expressionindicates an error. If a relative error is represented by r, Equation 26is obtained. Then, let be W_(gWi)≈W_(mWi), Equation 26 is modified intoEquation 27: $\begin{matrix}\left. {\frac{W_{effNa}}{W_{effWi}} \cdot} \middle| {\Delta \quad W} \middle| {< {r \cdot W_{effNa}}} \right. & \left( {{Eq}.\quad 26} \right) \\{W_{mWi} > \frac{\left| {\Delta \quad W} \right|}{r}} & \left( {{Eq}.\quad 27} \right)\end{matrix}$

Equation 27 imposes limitations upon the size of a wide transistor. Forinstance, when ΔW=0.1 μm and r=0.02, the mask channel width W_(mWi) of awide transistor is required to be greater than 5 μm, in order toaccurately extract the effective channel width of a narrow transistor.

Also, in the case where a channel narrowing DW is determined from(2·dW**−DW*), it is desirable to determine a mask channel width W_(mWi)in a similar manner.

Third Preferred Embodiment

A characteristic evaluation method for insulated gate type transistorsaccording to a third preferred embodiment will be described hereafter.In this method, a channel narrowing DW is extracted by using the draincurrents of linear areas in two insulated gate type transistors thathave the same mask channel length L_(m) and a different mask channelwidth W_(m).

The above characteristic evaluation method in the third preferredembodiment will be roughed out. As in the first preferred embodiment,there are firstly prepared two MOS transistors, each having the samechannel length L_(m) and a different mask channel width W_(m). Then, thethreshold voltage V_(thWi) of a wide transistor and the thresholdvoltage V_(thNa) of a narrow transistor are extrapolated fromI_(ds)−V_(gs) characteristic or the like. The threshold voltage V_(thNa)thus extracted is a first estimated value. Under the conditions that thegate overdrive V_(gt) of the wide transistor, i.e., a first gateoverdrive, is equal to the gate overdrive V_(gt) of the narrowtransistor, i.e., a second gate overdrive, a virtual point as describedlater is extracted in an X-Y plane whose X-axis is mask channel widthW_(m) and Y-axis is source-drain resistance R. This virtual point is notpresent as an actual measuring point, but is a virtual point on astraight line that passes through a first point whose X-coordinate isthe mask channel width W_(mWi) of the wide transistor and Y-coordinateis the source-drain resistance R_(Na) of the narrow transistor, and asecond point whose X-coordinate is the mask channel width W_(mNa) of thenarrow transistor and Y-coordinate is the source-drain resistance R_(Wi)of the wide transistor. Such a virtual point has the characteristicfeature that the change in source-drain resistance is approximately zeroeven when the first and second gate overdrives are finely changed.Therefore, as shown in FIG. 19, this virtual point is found as theintersection of two straight lines exhibiting the difference of δV_(gt)between the first and second gate overdrives. The X-coordinate (W_(m)coordinate) and Y-coordinate of the above intersection are representedby DW^(#) and R^(#), respectively. Note that the straight lines in thethird preferred embodiment contain curves that can be approximated to astraight line. In the event that a virtual point is located slightlyapart from the straight lines, a point in the vicinity of anintersection may be used.

The relationship of Equation 28 is established between the intersectioncoordinate (R^(#), DW^(#)) and the slope h of a straight line in FIG.19. In Equation 28, a prime indicates the first-order differentiation ofV_(gt).

R ^(#) ′=h·DW ^(#)′  (Eq. 28)

The values of DW^(#), (δ, V_(gtWi)), R^(#)′(δ, V_(gtWi)), and h(δ,V_(gtWi)) are found from the source-drain resistance of a narrowtransistor R_(Na)(V_(gtWi)+δ−V_(thNa)+V_(thWi)) and the source-drainresistance of a wide transistor R_(Wi)(V_(gtWi)). Hereat, δ is a shiftamount to be changed in calculating the difference between two truethreshold voltages V_(thWi), V_(thNa). When a shift amount δ is equal tothe threshold voltage difference between the wide and narrow transistors(V_(thNa)−V_(thWi)), the relationship of Equation 28 is established.Accordingly, the function F that is defined in Equation 29 is zero,irrespective of the gate overdrive V_(gt):

F(δ, V _(gtWi))=R ^(#)′(δ, V _(gtWi))−h(δ, V _(gtWi))·DW ^(#)′(δ, V_(gtWi))  (Eq. 29)

A shift amount δ is changed to determine the value of a true shiftamount δ₀ with which the standard deviation of function F is a minimumin a certain area of a gate overdrive V_(gt). Using the true shiftamount δ₀, the value dW** of X intercept is found by, for example,extrapolating straight lines as shown in FIG. 19. From the obtaineddW**, a channel narrowing DW is determined. An effective channel widthW_(eff) is a value that is obtained by reducing a channel narrowing DWfrom a mask channel width W_(m).

Referring to FIG. 20, extraction of the effective channel width W_(eff)of an MOS transistor will be described in detail.

FIG. 20 shows the steps in a characteristic evaluation method forinsulated gate type transistors according to the third preferredembodiment. The above steps are the same as those in FIG. 4 in the firstpreferred embodiment which are designated by the same reference numeral,except for step ST1.20. In step ST1.20, the function F shown in Equation29 is calculated. In step ST1.9, by using a calculation result obtainedin step ST1.20, a true shift amount δ₀ is determined from a shift amountδ with which the standard deviation calculated in step ST1.7 is aminimum. Steps ST1.10 and ST1.11 in which from the above true shiftamount, a channel narrowing DW and an effective channel width W_(eff)are determined δ₀, respectively, are the same as in the characteristicevaluation method of the first preferred embodiment as shown in FIG. 4.

Although a channel narrowing DW_(Na) is determined from dW** in stepST1.11, a channel narrowing DW(V_(gt)) that is obtained when the gateoverdrive V_(gt) is in the vicinity of zero may be determined as thevalue DW^(#) of W_(m) coordinate at an intersection.

Description will be now given of a concrete procedure to determine achannel narrowing DW and the like, from the standard deviation of thefunction F shown in Equation 29. In the characteristic evaluation methodof the third preferred embodiment, to reduce the uncertainty ofthreshold voltage extrapolation and, in particular, the error due to theuncertainty of the threshold voltage extrapolation of a transistorhaving a narrow channel width, the relationship of Equation 30 which is,for example, established between the value DW* of W_(m) coordinate at avirtual point and the value dW** of W_(m) intercept, is noted to apply avariation method. Here at, since the differentiation of an intersectioncoordinate (R^(#), DW^(#)) in Equation 29 may increase the error ofcalculated values, Equation 30 is used in place of Equation 29:$\begin{matrix}{{F\left( {\delta,V_{gtWi}} \right)} = {{{dW}^{**}\left( {\delta,V_{gtWi}} \right)} + {\frac{h\left( {\delta,V_{gtWi}} \right)}{h^{\prime}\left( {\delta,V_{gtWi}} \right)} \cdot {{dW}^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}} - {{DW}^{\#}\left( {\delta,V_{gtWi}} \right)}}} & \left( {{Eq}.\quad 30} \right)\end{matrix}$

Firstly, to a certain shift amount δ, DW^(#)(V_(gtWi), δ) anddW**(V_(gtWi), δ) are given by Equations 31 and 32, respectively, whererri and rai are defined in Equations 33 and 34, respectively, and theslope h of a straight line is given by Equation 35. $\begin{matrix}{{DW}^{\#} = \frac{W_{mNa} - {{rri} \cdot W_{mWi}}}{1 - {rri}}} & \left( {{Eq}.\quad 31} \right) \\{{dW}^{**} = \frac{W_{mNa} - {{rai} \cdot W_{mWi}}}{1 - {rai}}} & \left( {{Eq}.\quad 32} \right) \\{{{rri}\left( {V_{gtWi},\delta} \right)} \equiv \frac{R_{Wi}^{\prime}\left( V_{gtWi} \right)}{R_{Na}^{\prime}\left( {V_{gtWi} + \delta - V_{thNa} + V_{thWi}} \right)}} & \left( {{Eq}.\quad 33} \right) \\{{{rai}\left( {V_{gtWi},\delta} \right)} \equiv \frac{R_{Wi}\left( V_{gtWi} \right)}{R_{Na}\left( {V_{gtWi} + \delta - V_{thNa} + V_{thWi}} \right)}} & \left( {{Eq}.\quad 34} \right) \\{{h\left( {V_{gtWi},\delta} \right)} = \frac{{R_{Na}\left( {V_{gtWi} + \delta - V_{thNa} + V_{thWi}} \right)} - {R_{Wi}\left( V_{gtWi} \right)}}{W_{mWi} - W_{mNa}}} & \left( {{Eq}.\quad 35} \right)\end{matrix}$

A shift amount δ is changed to find the value DW^(#) of W_(m)coordinate, the value dW** of W_(m) intercept and its rate of changedW**′, as well as the resistance R per unit width and its rate of changeR′.

When a shift amount δ is equal to the threshold voltage difference δ₀between narrow and wide transistors, the function F defined in Equation30 is zero, irrespective of the gate overdrive V_(gtWi). Thus, let thevalue of a shift amount δ with which the standard deviation of thefunction F becomes a minimum in an area of a gate overdrive V_(gtWi) bea true shift amount δ₀ (see FIG. 21).

Then, let the value of dW** (V_(gt), δ₀) of W_(m) intercept which isobtained by using a true shift amount δ₀, be a channel narrowingDW(V_(gt)).

Although in the third preferred embodiment a true shift amount δ₀ isdetermined from the condition under which the standard deviation of thefunction F is a minimum, it may be determined from the condition underwhich the sum of values that are obtained by squaring each of thefunctions F to be found for discrete gate overdrives V_(gt), becomes aminimum. When calculating gate overdrive V_(gt) for about 20 points, thesum Z can be expressed by Equation 36: $\begin{matrix}{Z = {\sum\limits_{n = 1}^{20}\quad {F^{2}\left( V_{gtn} \right)}}} & \left( {{Eq}.\quad 36} \right)\end{matrix}$

Instead of Equation 30, any one of Equations 37 to 39 may be used tofind function F: $\begin{matrix}{{F\left( {\delta,V_{gtWi}} \right)} = {{\frac{h^{2}\left( {\delta,V_{gtWi}} \right)}{h^{\prime}\left( {\delta,V_{gtWi}} \right)} \cdot {{dW}^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}} - {R^{\#}\left( {\delta,V_{gtWi}} \right)}}} & \left( {{Eq}.\quad 37} \right) \\{{F\left( {\delta,V_{gtWi}} \right)} = {{R^{**}\left( {\delta,V_{gtWi}} \right)} - {\frac{h\left( {\delta,V_{gtWi}} \right)}{h^{\prime}\left( {\delta,V_{gtWi}} \right)} \cdot {R^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}} - {R^{\#}\left( {\delta,V_{gtWi}} \right)}}} & \left( {{Eq}.\quad 38} \right) \\{\quad {{F\left( {\delta,V_{gtWi}} \right)} = {\frac{R^{**^{\prime}}\left( {\delta,V_{gtWi}} \right)}{h^{\prime}\left( {\delta,V_{gtWi}} \right)} + {{DW}^{\#}\left( {\delta,V_{gtWi}} \right)}}}} & \left( {{Eq}.\quad 39} \right)\end{matrix}$

In Equations 38 and 39, R** is the value of a source-drain resistance Rwhen the value of a mask channel width W_(m) is set to be zero inR−W_(m) characteristic. Using mask channel width W_(m) to enter anX-axis and source-drain resistance R to enter a Y-axis, a R−W_(m)characteristic curve (straight line) is extrapolated to find the valueR** of a Y intercept and the value dW** of an X intercept which areobtained as X=0 and Y=0, respectively. The use of the value R** or dW**facilitates calculation. Although the accuracy remains unchanged withany one of Equations 30, and 37 to 39, it is necessary to calculate R**when using Equation 38 or 39. Thus, Equation 30 or 37 is preferred.

Although in the third preferred embodiment the value dW** of W_(m)intercept obtained when a true shift amount δ₀ is used is employed asthe value of a channel narrowing DW, the value of a channel narrowing DWobtained when a gate overdrive V_(gt) is in the vicinity of zero may begiven by the average of the values DW^(#) in the neighborhood where thevalue DW^(#) of W_(m) coordinate of an intersection has a minimum value(see FIG. 22). Since DW^(#) has a stationary point when the gateoverdrive V_(gt) has a value in the vicinity of zero, it is possible todetermine the value of a channel narrowing DW at higher accuracy thanthe case of using the value dW* of W_(m) intercept.

Referring to FIG. 23, a characteristic evaluation apparatus forinsulated gate type transistors according to the third preferredembodiment can be constructed by partially modifying the calculationsection 6 of the characteristic evaluation apparatus 1 of the firstpreferred embodiment in FIG. 8. Specifically, the parts to be modifiedare an extraction section 12B that extracts an intersection coordinate(DW^(#), R^(#)) as the coordinate of a virtual point, the value dW** ofW_(m) intercept, the value R** of R intercept, and the slope h of astraight line in the intersection coordinate; a true shift amountdetermination section 13B that determines a true shift amount δ₀ fromthe values extracted in the extraction section 12B; and a channelnarrowing determination section 14B that determines a channel narrowingby using a value giving a true shift amount δ₀ which is selected fromamong the values extracted in the extraction section 12B. Othercomponents of the calculation section 6B in FIG. 23 are the same asthose in the first preferred embodiment. The extraction section 12Bfurther extracts the rate of change dDW^(#)/dV_(gt), dR^(#)/dV_(gt) ofan intersection coordinate (DW^(#), R^(#)) and the slope h of acharacteristic curve in an area Ω with respect to each shift amount δ,by using the value of a mask channel width W_(m) provided from an inputsection 5, the measurement data of source-drain current I_(ds) andgate-source voltage V_(gt) that are provided from a control section 4.The true shift amount determination section 13B determines a virtualshift amount δ₀ with which the standard deviation of the function Fshown in Equation 29 becomes a minimum for the area Ω, by using the rateof change dDW^(#)/dV_(gt) of the W_(m) coordinate of an intersection,the rate of change dR^(#)/dV_(gt) of R coordinate of the intersection,and the slope h of the characteristic curve which have been extracted inthe extraction 12B. Upon determination of a true shift amount δ₀, theextraction section 12B outputs the true shift amount δ₀ or the valueDW^(#) of W_(m) coordinate of the corresponding intersection and valuedW** of W_(m) intercept, to a channel narrowing determination section14B. The section 14B determines a channel narrowing DW from the valuedW** of W_(m) intercept or the value DW^(#) of W_(m) coordinate in avirtual point, and performs the calculation shown in Equation 7, todetermine an effective channel width W_(eff).

Referring again to FIG. 9, the characteristic evaluation for insulatedgate type transistors as described in the third preferred embodiment isattainable by making a computer to read an evaluation program 30 forevaluating insulated gate type transistors from a recording mediumstoring the program 30, in accordance with the procedure in FIG. 20 asdescribed in the third preferred embodiment.

A method of manufacturing an insulted gate type transistor according tothe third preferred embodiment can be implemented by employing, in stepST52 shown in FIG. 10, the evaluation method of the third preferredembodiment in place of that of the first preferred embodiment. Thisresults in the same effects as in the case where the evaluation methodof the first preferred embodiment is applied to a manufacturing method.

Fourth Preferred Embodiment

A characteristic evaluation method for insulated gate type transistorsaccording to a fourth preferred embodiment will be outlined by referringto FIG. 24. FIG. 24 is a graph showing the relationship between DW^(#)and gate overdrive V_(gt) that are found by the characteristicevaluation method for insulated gate type transistors according to thefourth preferred embodiment. This graph shows the change in the valueDW^(#) of W_(m) coordinate of an intersection when a true thresholdvoltage is used for three narrow transistors having a different maskchannel width W_(mNa). Note that the mask channel width W_(mWi) of awide transistor that serves as a reference in extracting the valueDW^(#) of W_(m) coordinate for these transistors, is set to the samevalue.

As shown by comparison of FIG. 24 with FIG. 25, if the value of a shiftamount δ derives from a shift amount δ₀, the shape of a V_(gt)−DW^(#)characteristic curve changes, whereas even if the value of a maskchannel width W_(mNa) changes somewhat, the shape of a V_(gt)−DW^(#)characteristic curve remains unchanged. Hence, as to other transistorhaving a different mask channel width W_(m), it is also possible toextract the true threshold voltage of a narrow transistor by finding outone characteristic curve which coincides with that in this graph whenthe gate overdrive V_(gt) ranges from 0.3 to 1.2 V, for example. In thefourth preferred embodiment, first and second gate overdrives and firstto fourth estimated values are defined as in the third preferredembodiment.

One example of the characteristic evaluation method for insulated gatetype transistors according to the fourth preferred embodiment will bedescribed by referring to FIG. 26. In the method shown in FIG. 26, fromcharacteristic curves that change variously depending on the estimatedvalue of a threshold voltage V_(thNa), i.e., a first estimated value,the characteristic curve in FIG. 24 is extracted based on the fact thatthe standard deviation of the curve is small in the range of 0.2 to 0.6V, for example. Since in the evaluation method of the fourth preferredembodiment, the true threshold voltage δ₀ of a narrow transistor isdetermined by utilizing the dependence of the value DW^(#) of W_(m)coordinate on a gate overdrive V_(gt), the true threshold voltage δ₀ isdetermined in a manner similar to that in the third preferredembodiment.

The procedure of extracting an effective channel width W_(eff) in thecharacteristic evaluation method of the fourth preferred embodiment isthe same as that of the third preferred embodiment, except for stepsST1.30 to ST1.34 in FIG. 26, which correspond to steps ST1.20, ST1.7 andST1.9 to ST1.11 in FIG. 20, respectively.

In the loop composed of steps ST1.4 to ST1.8, at step ST1.30 the valueDW^(#) of W_(m) coordinate at a virtual point is found. That is, thevalues DW^(#) of about twenty different gate overdrives V_(gtn) for eachshift amount δ are found. At step ST1.31, the average of the twentyDW^(#) values of DW^(#)(δ, V_(gt1)) to DW^(#)(δ, V_(gtn)), and thestandard deviation σ[DW^(#)] are calculated.

After repeat calculation for each shift amount δ (steps ST1.14 to ST1.8)is terminated, at step ST1.32, a shit amount δ₀ for giving a channelnarrowing DW is estimated, with which the standard deviation σ becomes aminimum. At step ST1.33, the channel narrowing DW is given by theaverage of the values DW^(#) of W_(m) coordinates at a virtual pointwhen a shit amount is δ₀. At step ST1.34, an effective channel widthW_(eff) is determined by the difference between a mask channel width andthe channel narrowing DW.

Referring to FIG. 27, description will be now given of a characteristicevaluation apparatus for insulated gate type transistors according tothe fourth preferred embodiment. A characteristic evaluation apparatusfor insulated gate type transistors 1C shown in FIG. 27 is connected toa measuring device 3 for measuring an object under test 2, like thecharacteristic evaluation apparatus 1B of the third preferred embodimentas shown in FIG. 23. In the construction of the characteristicevaluation apparatus 1C, the same reference numerals have been retainedfor similar parts which have the same functions as in the apparatus 1Bof FIG. 23. That is, the characteristic evaluation apparatus 1C has thesame structure as the apparatus 1B, except for an extraction section12C, a true shift amount determination section 13C and a channelnarrowing determination section 14A in a calculation section 6C.

The extraction section 12C of the characteristic evaluation apparatus 1Cfinds an intersection coordinate (DW^(#), R^(#)) by changing a gateoverdrive V_(gt) in an area Ω. The true shit amount determinationsection 13C finds a standard deviation σ[DW^(#)] from the value of theintersection coordinate (DW^(#), R^(#)) in the area Ω, to determine atrue shift amount δ₀. The extraction section 12C outputs the true shiftamount δ₀ and the value DW^(#) of W_(m) coordinate at the correspondingintersection or the value dW** of W_(m) intercept, to the channelnarrowing determination section 14C. The channel narrowing section 14Cdetermines a channel narrowing DW from the average of the values DW^(#)of W_(m) coordinates at virtual points within the area Ω for the trueshift amount δ₀, e.g., in the range of 0.2≦V_(gt)≦0.6. Alternatively,the section 14C determines the value dW** of W_(m) intercept related tothe true shift amount δ₀, as a channel narrowing DW.

Referring again to FIG. 9, the characteristic evaluation for insulatedgate type transistors as described in the fourth preferred embodiment isattainable by making a computer to read an evaluation program 30 forevaluating insulated gate type transistors from a recording mediumstoring the program 30, in accordance with the procedure in FIG. 20 asdescribed in the fourth preferred embodiment.

A method of manufacturing an insulted gate type transistor according tothe fourth preferred embodiment can be implemented by employing, in stepST52 shown in FIG. 10, the evaluation method of the fourth preferredembodiment in place of that of the first preferred embodiment. Thisresults in the same effects as in the case where the evaluation methodof the first preferred embodiment is applied to a manufacturing method.

Although in the fourth preferred embodiment, a channel narrowing DW isdetermined so as to minimize the standard deviation σ[DW^(#)] of thevalue DW^(#) of W_(m) coordinate at an intersection or the standarddeviation σ[dW**] of the value dW** of W_(m) intercept, itsdetermination method is not limited to the above. For instance, thethreshold voltage V_(thNa) of a narrow transistor may be determined byselecting a characteristic curve in which the value DW** of W_(m)coordinate at an intersection is best converged on a fixed value whenthe gate overdrive V_(gt) is within a predetermined range.

When the mask channel width W_(mNa) of a narrow transistor issufficiently smaller than the mask channel width W_(mWi) of a widetransistor (W_(mNa)<<W_(mWi)), Equation 31 is approximated as shown inEquation 40. Accordingly, a channel narrowing DW may be determined sothat the standard deviation of the value of Equation 40 is a minimum:

 DW ^(#) ≈W _(mNa) −rri·W _(mWi)  (Eq. 40)

Alternatively, in Equation 40 a channel narrowing DW may be determinedunder the condition that the standard deviation of a variable rri is aminimum, because mask channel widths W_(mWi) and W_(mNa) are bothconstants.

Alternatively, since the condition that the standard deviation of thevariation rri is a minimum is approximately equal to that the standarddeviation of its inverse number rri⁻¹ is a minimum, a channel narrowingDW may be determined from the standard deviation of the inverse numberrri⁻¹.

In the channel narrowing DW extraction according to the third or fourthpreferred embodiment, when the mask cannel width W_(mNa) of a narrowtransistor is significantly smaller than the mask channel width W_(mWi)of a wide transistor (i.e., W_(mNa)<<W_(mWi)), the difference betweenthe mask channel width W_(mwi) and a gate finished width W_(gWi) hardlyaffects on determination of the value DW* of W_(m) coordinate at avirtual point, thereby determines the channel narrowing DW of the narrowtransistor at high accuracy. For instance, to evaluate device or circuitperformance on the level of not more than 1.0 μm in pattern width, it isrequired to extract the channel narrowing DW of each transistor. Forsuch an extraction, there are used two transistors, i.e., a narrowtransistor and a wide transistor serving as a reference. In this case,the difference between a gate finished width W_(g) and a mask channelwidth W_(m) depends on the transistor, causing errors. Thus, descriptionwill be now given of such errors. The value DW^(#) of W_(m) coordinateat a virtual point when a mask channel width W_(m) is used is given byEquation 41: $\begin{matrix}{{DW}^{\#} = {\left( {W_{mNa} - {\frac{R_{Wi}^{\prime}}{R_{Na}^{\prime}} \cdot W_{mWi}}} \right) \cdot \left( {1 - \frac{R_{Wi}^{\prime}}{R_{Na}^{\prime}}} \right)^{- 1}}} & \left( {{Eq}.\quad 41} \right)\end{matrix}$

If W_(g) coordinate of an intersection in a plane formed by gatefinished width and source-drain conductance (i.e., a W_(g)−R plane) isrepresented by DW_(g) ^(#), the following Equation 42 is obtained:$\begin{matrix}{{DW}_{g}^{\#} = {\left( {W_{gNa} - {\frac{R_{Wi}^{\prime}}{R_{Na}^{\prime}} \cdot W_{gWi}}} \right) \cdot \left( {1 - \frac{R_{Wi}^{\prime}}{R_{Na}^{\prime}}} \right)^{- 1}}} & \left( {{Eq}.\quad 42} \right)\end{matrix}$

If the difference between a gate finished width W_(g) and a mask channelwidth W_(m) is represented by ΔW, the difference between the gatefinished width W_(gWi) and mask channel width W_(mWi) of a widetransistor, and the difference between the gate finished width W_(gNa)and a mask channel width W_(mNa) of a narrow transistor, are representedby ΔW_(Wi) and ΔW_(Na), respectively. Therefore, the relationships ofEquations 43 and 44 are established. Then, from Equations 41 to 44, thedifference between the value DW** of W_(m) coordinate and the valueDW_(g)* of W_(g) coordinate at an intersection is expressed by Equation45, where ΔW is defined in Equation 46:

W _(gWi) =W _(mWi) +ΔW _(Wi)  (Eq. 43)

W _(gNa) =W _(mNa) +ΔW _(Na)  (Eq. 44)

$\begin{matrix}\begin{matrix}{{{DW}^{\#} - {DW}_{g}^{\#}} = \quad {{{- \Delta}\quad W_{Na}} + {{\frac{R_{Wi}^{\prime}}{R_{Na}^{\prime}} \cdot \left( {1 - \frac{R_{Wi}^{\prime}}{R_{Na}^{\prime}}} \right)^{- 1} \cdot \Delta}\quad W}}} \\{\approx \quad {{{- \Delta}\quad W_{Na}} + {{\frac{G_{Wi}^{\prime}}{R_{Na}^{\prime}} \cdot \Delta}\quad W}}} \\{\approx \quad {{{- \Delta}\quad W_{Na}} + {{\frac{W_{effNa}}{W_{effWi}} \cdot \Delta}\quad W}}}\end{matrix} & \left( {{Eq}.\quad 45} \right)\end{matrix}$

 ΔW=ΔW _(Wi) −ΔW _(Na)  (Eq. 46)

Equations 43 and 44 show that the effective channel width W_(eff) of anarrow transistor is extracted when the relationship W_(mNa)<<W_(mWi) isestablished. In Equation 45, the second term of the last expressionindicates an error. If a relative error is represented by r, it resultsin Equation 26. Therefore, again in the third and fourth preferredembodiments, to make a relative error smaller than the desired value,the same limitations are imposed upon the mask channel width W_(gWi) ofa wide transistor, as in the first and second preferred embodiments.

Consider now the influence of unequal channel lengths due to theirregularity of finished polygate. Source-drain resistance R_(tot) isdefined in Equation 47, where g is a channel sheet resistance:$\begin{matrix}{R = {{\frac{L_{eff}}{W_{eff}} \cdot g} + R_{sd}}} & \left( {{Eq}.\quad 47} \right)\end{matrix}$

Let the difference in the channel length L between a narrow transistorand a wide transistor be ΔL (=L_(effNa)−L_(effWi)) Equations 47 can bemodified into Equation 48: $\begin{matrix}{R \approx {{\frac{L_{effWi}}{W_{effNa} \cdot \left( {1 - \frac{\Delta \quad L}{L_{effWi}}} \right)} \cdot g} + R_{sd}}} & \left( {{Eq}.\quad 48} \right)\end{matrix}$

Supposing a sheet resistance g is independent of an effective channellength L_(eff), Equation 48 shows that an effective channel lengthL_(effNa) appears to be increased by a factor of (1−ΔL/L_(effWi)). Now,expressing a relative error by r, an error Δr is expressed by Equation49: $\begin{matrix}{{W_{effNa} \cdot \frac{{\Delta \quad L}}{L_{effWi}}} < {r \cdot W_{effNa}}} & \left( {{Eq}.\quad 49} \right)\end{matrix}$

Supposing that an effective channel length L_(effWi) is approximatelyequal to a mask channel length L_(mWi), Equation 49 can be modified intoEquation 50: $\begin{matrix}{L_{mWi} > \frac{{\Delta \quad L}}{r}} & \left( {{Eq}.\quad 50} \right)\end{matrix}$

Equation 50 imposes limitations upon the mask channel length L_(mWi) ofa wide transistor to be used in extraction. For instance, when ΔL=0.1 μmand r=0.02, the mask channel width W_(mWi) of a wide transistor isrequired to be greater than 5 μm, in order to accurately extract theeffective channel width of a narrow transistor.

Description will be now given of the case where the characteristicevaluation method for insulated gate type transistors according to thefirst preferred embodiment (hereinafter referred to as Gm method) orthat of the third preferred embodiment (referred to as Rm method) isapplied to a MOS transistor having a mask channel width W_(m) of 0.36 μmand a mask channel length L_(m) of 20.4 μm. FIG. 28 gives a comparisonamong the channel narrowing DW (obtained by Gm method), DW (by Rmmethod), and DW (by Chia method). Both Gm and Rm methods provide nearlythe same result. Since it is generally difficult to accurately determinea threshold voltage V_(th), Gm method and Rm method ensure more accuratechannel narrowing DW than Chia method.

Then, it is checked how the value dW* of W_(m) intercept and the valuesDW*, DW^(#) of W coordinate at an intersection depend on the gateoverdrive V_(gt) in the vicinity of zero. Now, expanding the channelnarrowing DW, the slope h of a straight line and the inverse number g(g=1/f) of the slope f of the straight line, to the power of a gateoverdrive V_(gt), Equations 51 to 53 are obtained where DWG1, DWG2, andA to D are an arbitrary constant:

DW=δW−DWG1·V _(gt) −DWG2·V _(gt) ² +O(V _(gt) ³)  (Eq. 51)

$\begin{matrix}{h = {\frac{A}{V_{gt}} + B + {O\left( V_{gt} \right)}}} & \left( {{Eq}.\quad 52} \right) \\{g = {\frac{C}{V_{gt}} + D + {O\left( V_{gt} \right)}}} & \left( {{Eq}.\quad 53} \right)\end{matrix}$

In this case, dW**, DW* and DW^(#) are expanded as follows:$\begin{matrix}{{dW}^{**} \approx {{\delta \quad W} - {{DWG1} \cdot {DWG2} \cdot V_{gt}^{2}} + {O\left( V_{gt}^{3} \right)}}} & \left( {{Eq}.\quad 54} \right) \\{{DW}^{*} \approx {{\delta \quad W} - {2 \cdot {DWG1} \cdot V_{gt}} - {\left( {{3 \cdot {DWG2}} + {\frac{D}{C} \cdot {DWG1}}} \right) \cdot V_{gt}^{2}} + {O\left( V_{gt}^{3} \right)}}} & \left( {{Eq}.\quad 55} \right) \\{{dW}^{\#} \approx {{\delta \quad W} + {\left( {{DWG2} + {\frac{B}{A} \cdot {DWG1}}} \right) \cdot V_{gt}^{2}} + {O\left( V_{gt}^{3} \right)}}} & \left( {{Eq}.\quad 56} \right)\end{matrix}$

Equations 54 to 56 indicate the following matters. When dW**, DW* andDW^(#) are brought to near zero, they all converge on δW. When DWG1 andDWG2 are both positive numbers, DW* decreases rapidly than dW** as thegate overdrive V_(gt) increases. DW^(#) has a stationary point atV_(gt)=0, and increases by the square of V_(gt) as the gate overdriveV_(gt) increases. These indicate that the results given in FIGS. 6 and22 are correct.

Also, the presence of the stationary point at V_(gt)=0 suggests thepossibility that δW is determined so that DW^(#) is constant when V_(gt)is in the vicinity of zero. This is the case where “shift and ratiomethod” is applied to the extraction of a channel narrowing DW (thismethod is described, for example, in “A New “Shift and Ratio” Method forMOSFT Channel Length Extraction,” IEEE Elect. Dev. Lett., EDL-13(5),p.267, 1992, by Y. Taur et al.). This method actually gives propervalues, however, its extraction result depends greatly on the area of agate overdrive V_(gt) for calculation (see FIG. 29). On the other hand,both Rm method and Gm method are independent of the area of a gateoverdrive V_(gt) for calculation, and also can give nearly the sameresult.

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

I claim:
 1. A method of manufacturing insulated gate type transistors,comprising the steps of: forming at least two insulated gate typetransistors that differ from each other only in mask channel width;measuring drain current characteristics of said two insulated gate typetransistors by changing a gate voltage and a source-drain voltage;determining an effective channel width of said two insulated gate typetransistors using a predetermined characteristic evaluation method forinsulated gate type transistors; and judging whether said effectivechannel width satisfies a specification, wherein one of said at leasttwo insulated gate type transistors having a wider mask channel width isdefined as a first insulated gate type transistor and the other having amore narrow mask channel width is defined as a second insulated gatetype transistor, said predetermined characteristic evaluation method forinsulted gate type transistors comprising steps of: extracting athreshold voltage of said first transistor, estimating the thresholdvoltage of said second transistor, and employing a value as estimated asa first estimated value; (i) defining a difference between a gatevoltage of said first transistor and said extracted threshold voltage ofsaid first transistor as a first gate overdrive, and defining adifference between a gate voltage of said second transistor and saidfirst estimated value as a second gate overdrive, (ii) under thecondition that said first and second gate overdrives are the same in anX-Y plane whose X-axis is said mask channel width and whose Y-axis issource-drain resistance, estimating and extracting a virtual point atwhich a change in Y coordinate value to be approximately zero even ifsaid first and second gate overdrives are finely changed from points ona straight line passing through a first point whose X coordinate is saidmask channel width of said first transistor and whose Y coordinate issaid source-drain resistance of said second transistor, and a secondpoint whose X coordinate is said mask channel width of said secondtransistor and whose Y coordinate is said source-drain resistance ofsaid first transistor, (iii) defining values of the X coordinate and theY coordinate at said virtual points as second and third estimatedvalues, respectively, and (iv) extracting a slope of said straight lineat said virtual points and employing a value of said slope as a fourthestimated value; determining a true threshold voltage of said secondtransistor by using said first to fourth estimated values; anddetermining a difference between said mask channel width and aneffective channel width based on said true threshold voltage.